cocotb_wrapper.axi.AxiLiteRam

class cocotb_wrapper.axi.AxiLiteRam(bus_prefix, clk, rst, reset_active_level, size)

A Wrapper around cocotbext-axi AXI-Lite RAM.

Todo

Add a usage example.

Parameters:

• bus_prefix (str) –

• clk (str) –

• rst (str) –

• reset_active_level (int) –

• size (int) –

__init__(bus_prefix, clk, rst, reset_active_level, size)

Initialize an instance.

Parameters:

• bus_prefix (str) – The prefix of signals belonging to the source bus

• tdata_width_bits – The width of tdata in bits

• clk (str) – The name of the clock

• rst (str) – The name of the reset

• reset_active_level (int) – 1 if active high 0 if active low

• size (int) – The memory size in bytes

Methods

disable()	Disable the AXI-Lite RAM.
enable()	Enable the AXI-Lite RAM.
hexdump(address, length[, prefix])	Dump the content of the RAM to the stdout.
read(address, length)	Read length bytes from address.
set_backpressure_generator(generator)	Toggle pauses on the read bus lanes given a generator function.
set_idle_generator(generator)	Toggle pauses on the write bus lanes given a generator function.
setup(dut)	Setup the AXI-Lite RAM.
write(address, data)	Write data to the address.